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Multi-Dielectric Band Diagram Program

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“My students and I have found the Boise State Band Diagram program, developed by Prof. Bill Knowlton and one of his graduate students, Ricki Southwick, to be extremely useful in dealing with a wide array of device physics problems. We have utilized the Boise State program in the preparation of multiple proposals, many conference presentations, and in multiple refereed journal articles. We’ve used it in our recent work on energy resolved spin dependent trap assisted tunneling, the negative bias temperature instability, high dielectric constant materials on silicon, and ultra-high frequency MIM diodes. The Southwick/Knowlton program has been an immensely helpful tool in my laboratory.”

– Pat Lenahan, Distinguished Professor, Dept. of Engineering Science and Mechanics, Penn State University

“The BSU Band diagram program is not only an excellent tool for illustrating concepts in the classroom, but it has also been invaluable to my research group for quickly producing accurate first order band diagrams of, for example, M/I/M and M/I/I/M structures.”

– John F. Conley, Jr., Professor, School of Electrical Engineering and Computer Science, Oregon State University

Citing Publications

The following journal publications have cited the Band Diagram Program as a reference, and have used its features to complement their research.

  • Lee, D.U., H.J. Lee, E.K. Kim, H.-W. You and W.-J. Cho, Low operation voltage and high thermal stability of a WSi2 nanocrystal memory device using an Al2O3/HfO2/Al2O3 tunnel layer. Applied Physics Letters, 2012. 100(7): p. 072901-4.
  • Nikolaou, N., P. Dimitrakis, P. Normand, V. Ioannou-Sougleridis, K. Giannakopoulos, K. Mergia, K. Kukli, J. Niinistöd, M. Ritalad and M. Leskeläd, Influence of atomic layer deposition chemistry on high-k dielectrics for charge trapping memories. Solid-State Electronics, 2012. 68(0): p. 38-47.
  • Lee, D.U., H.J. Lee, E.K. Kim, H.-W. You and W.-J. Cho, Charge loss in WSi2 nanocrystals nonvolatile memory with SiO2/Si3N4/SiO2 tunnel layer. Current Applied Physics, 2011. In Press, Corrected Proof.
  • Congedo, G., S. Spiga, U. Russo, A. Lamperti, O. Salicio, E. Cianci and M. Fanciulli, Evaluation of DyScOx as an alternative blocking dielectric in TANOS memories with Si3N4 or Si-rich SiN charge trapping layers. Journal of Vacuum Science & Technology B, 2011. 29(1): p. 01AE04-7.
  • Kim, H.D., H.M. An, E.B. Lee and T.G. Kim, Stable Bipolar Resistive Switching Characteristics and Resistive Switching Mechanisms Observed in Aluminum Nitride-based ReRAM Devices. Electron Devices, IEEE Transactions on, 2011. 58(10): p. 3566-3573.
  • Lee, D., E. Kim, W.-J. Cho and Y.-H. Kim, Resistance switching properties of In2O3 nanocrystals memory device with organic and inorganic hybrid structure. Applied Physics A: Materials Science & Processing, 2011. 102(4): p. 933-938.
  • Lee, H.J., D.U. Lee, E.K. Kim, H.-W. You and W.-J. Cho, Electrical characteristics of WSi2 nanocrystal capacitors with barrier-engineered high-k tunnel layers. Japenese Journal of Applied Physics, 2011. 50: p. 06GF13 (1-4).
  • Lenahan, P.M., C.J. Cochrane, J.P. Campbell and J.T. Ryan, Electrically Detected Magnetic Resonance in Dielectric Semiconductor Systems of Current Interest. ECS Transactions, 2011. 35(4): p. 605-627.
  • Seguini, G., S. Schamm-Chardon, P. Pellegrino and M. Perego, The energy band alignment of Si nanocrystals in SiO2. Applied Physics Letters, 2011. 99(8): p. 082107.
  • Yujeong, S., H.-M. An, H.-D. Kim, I.R. Hwang, S.H. Hong, B.H. Park and T.G. Kim, High-speed and low-voltage performance in a charge-trapping flash memory using a NiO tunnel junction. Journal of Physics D: Applied Physics, 2011. 44(15): p. 155105 (6pages).
  • Cho, H.-J., S. Younghwan, O. Byoungchan, L. Sanghoon, L. Jong-Ho, P. Byung-Gook and S. Hyungcheol, Observation of Slow Oxide Traps at MOSFETs Having Metal/High-k Gate Dielectric Stack in Accumulation Mode. Electron Devices, IEEE Transactions on, 2010. 57(10): p. 2697-2703.
  • Cho, C.-H., B.-H. Kim, S.-K. Kim and S.-J. Park, Characterization of electronic structure of silicon nanocrystals in silicon nitride by capacitance spectroscopy. Applied Physics Letters, 2010. 96(22): p. 223110-3.
  • Kang, C.Y., Barrier engineering in metal-aluminum oxide-nitride-oxide-silicon (MANOS) flash memory: Invited. Current Applied Physics, 2010. 10(1, Supplement 1): p. e27-e31.
  • Raghavan, N., K.L. Pey, W.H. Liu and X. Li. New statistical model to decode the reliability and weibull slope of high-κ and interfacial layer in a dual layer dielectric stack. in Reliability Physics Symposium (IRPS), 2010 IEEE International. 2010.
  • Ryan, J.T., P.M. Lenahan, A.T. Krishnan and S. Krishnan, Spin dependent tunneling spectroscopy in 1.2 nm dielectrics. Journal of Applied Physics, 2010. 108(6): p. 064511-6.
  • Ryan, J.T., P.M. Lenahan, A.T. Krishnan and S. Krishnan, Energy resolved spin dependent trap assisted tunneling investigation of silc related defects, in IEEE International Reliability Physics Symposium. 2010, IEEE. p. 1122-1125.
  • Southwick III, Richard, Ph.D. Dissertation in Electrical & Computer Engineering, “An Investigation of Carrier Transport in Hafnium Oxide/Silicon Dioxide MOS Gate Dielectric Stacks from 5.6-400K.”(December 2010)
  • Southwick III, Richard G., Justin C. Reed, Christopher Buu, Ross Butler, Gennadi Bersuker, and William B. Knowlton, “Limitations of Poole-Frenkel Conduction in Bilayer HfO2/SiO2 MOS Devices.” IEEE Transactions on Device and Materials Reliability, 10(2) (2010) pp. 201-207.
  • Young, C.D., D. Heh, R. Choi, B.H. Lee and G. Bersuker, The Pulsed Id-Vg methodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics. JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2010. 10(2): p. 79-99.
  • Gurfinkel, M., J.S. Suehle and Y. Shapira, Enhanced gate induced drain leakage current in HfO2 MOSFETs. Microelectronic Engineering, 2009. 86(11): p. 2157-2160.
  • Ryan, J.T., P.M. Lenahan, A.T. Krishnan and S. Krishnan, Investigation of SILC via Energy Resolved spin dependent tunneling spectroscopy, in IEEE International Integrated Reliability Workshop. 2009, IEEE: S. Lake Tahoe, CA p. 1 – 4
  • Sanghoon, L., C. Heung-Jae, S. Younghwan, L. Dong Seup and S. Hyungcheol. Characterization of oxide traps leading to RTN in high-k and metal gate MOSFETs. in Electron Devices Meeting (IEDM), 2009 IEEE International. 2009.
  • Dawei, H., P.D. Kirsch, C.D. Young and G. Bersuker. A new dielectric degradation phenomenon in nMOS high-k devices under positive bias stress. in IEEE International Reliability Physics Symposium. 2008. Phoenix, AZ IEEE.
  • Southwick III, Richard, Master of Science Thesis, Electrical & Computer Engineering, “Novel approach to reliability studies of hafnium oxide in MOS devices”, (March 2008)