Our research focuses on designing state-of-the-art computer architectures at both transistor and RTL levels by introducing low-power, high-precision logic blocks and exploring emerging memory technologies. This approach addresses the pressing need for energy-efficient, high-performance processing of AI workloads. By developing specialized logic circuits, we enhance computational precision and speed while minimizing power consumption. Additionally, we investigate various memory technologies, including non-volatile and analog circuit-based memory, to improve data retention and access times. These memory solutions are essential for reducing bottlenecks associated with traditional memory units and supporting scalable, low-power computing. We aim to drive the next generation of AI accelerators, meeting the computational and energy efficiency demands of advanced AI applications.
Research Topics
Shifter-based processing elements for massively parallel computing applications
This research project aims to facilitate transformative change to the traditional Von-Neuman computer and graphics processing unit architectures by developing and designing energy-efficient shifter-based processing elements (PE) for high memory and compute-bound applications such as artificial intelligence (AI) workloads.
Transformative power reduction through novel artificial intelligence algorithms for shifter-based memory-centric computing architecture
This research project will tackle the inefficiencies in the current training algorithm and its associated hardware architecture. The project goals are twofold: in the fundamental knowledge part, this project aims to investigate the significant bottleneck of AI-model training and develop a novel training algorithm to decrease memory needs by half. On the engineering innovation side, the research will introduce shifter-based parallel processing elements (PEs) with efficient buffer management systems within the processor-in-memory (PIM) architecture to improve speed, power, and efficiency.